1. Field of the Invention
This invention relates generally to the field of integrated circuit design and, more particularly, to the design of an interface circuit between two voltage supply domains.
2. Description of the Related Art
The proliferation of digital devices in everyday life has resulted in integrated circuits not only being used in computer equipment but also in a variety of other electronics systems. While most early digital equipment comprising integrated circuits relied on specific voltage levels, e.g. 5.0V at first, then 3.3V, for a number of reasons it has become desirable to further lower the supply voltage levels used in powering many of today's devices. For example, instead of using a 3.3V supply voltage to power a specific device, a lower voltage, e.g. 1.1V may be used. However, the reduction of the supply voltage levels in various systems and/or devices has not been universally implemented, and many disparate systems and/or system components are oftentimes designed to operate according to different supply voltages. For example, a microprocessor in a system may operate according to a reduced supply voltage, while other peripheral devices such as memory modules may still operate using a relatively higher supply voltage.
In general, integrated circuits (ICs) are now frequently built to operate at different supply voltage levels. For example, input/output (I/O) circuits may use higher supply voltages than circuits configured within the core of a processor. Higher supply voltages may frequently be desirable to interface properly with other system and/or circuit components. I/O pads may sometimes require higher supply voltage levels to drive heavily loaded output signals at an acceptable speed, for example. Lower supply voltage levels are typically desirable in the core of an IC to reduce power consumption and facilitate the use of smaller transistors, thereby reducing the overall die size. In certain cases, however, different voltage levels may also be applied to sections of the circuit comprised in the core. For example, when programming non-volatile memories such as programmable read-only memories in a programmable logic device, the voltage applied to the memory cells may be higher than the supply voltage used during user operation of the programmable logic device. Oftentimes, higher supply voltages may be required during power-up of a device, when the power level provided by the regular lower voltage supply might be too low for the device to properly reset itself.
In addition to lowering the overall voltage levels in ICs and various digital systems, various techniques aimed at temporarily lowering power during operation have also been introduced. Accordingly, various new modes of operation have been incorporated into multi-core processors to reduce power usage when the processor is not in full operation. For example, currently known CPU ACPI (Advanced Configuration and Power Interface) and ACPI-based low-power states (C1-C5) are very instrumental in eliminating dynamic power consumption and reducing the CPU static power. Another technique, sometimes called “drowsy mode”, features leaving the power supply turned on while lowering the actual voltage level, thereby reducing the voltage gap, or voltage difference between the operating “high” and “low” levels compared to normal operation.
Level shifter circuits have been introduced to accommodate transferring data between various supply voltage domains. However, the various different modes of operation can oftentimes pose problems and might limit the manner in which level shifters can be used. For example, it may be critical for the voltage level shifters to retain the proper state of the signals corresponding to the transferred data. Minimizing current consumption is also an important factor. FIG. 1 shows a typical configuration in which a first signal (Signal 1) is provided from logic circuit 102, operating according to a first supply voltage Vdd1, to logic circuit 104, operating according to a second supply voltage Vdd2, using a level shifter circuit 110. Similarly, another signal (Signal 2) may be provided from logic circuit 104 to logic circuit 102, using a level shifter circuit 112. FIG. 2 shows voltage and current diagrams corresponding to the power rails Vdd1 and Vdd2. If Vdd1 is powered down (turned off) while Vdd2 remains turned on, as shown in voltage graph 106, signal 1 may lose its state and become undefined. This would result from the output of level shifter circuit 110 entering an unknown state (sometimes referred to as a “floating output” or “floating signal”) due to the transistors that drive the output of level shifter 110 turning off in response to losing power from Vdd1. The floating signal can cause a rather large crowbar current to flow in logic circuit 104, as shown in current graph 108. The same would hold for Signal 2 if Vdd2 were turned off and Vdd1 remained turned on, while providing Signal 2 from logic circuit 104 to logic circuit 102.
One solution for avoiding crowbar current has been the use of reset generators working in concert with the level shifter circuit. Reset generators are usually configured to trigger at a reference voltage on the falling edge of the power supply that is powered off (i.e. Vdd1 in FIG. 1), when the power supply is powered off, and register the values in the second power supply domain (i.e. in the Vdd2 domain in FIG. 1). The reset generator may be used to force the signals on the interface to zero, thereby eliminating the floating signal at the output of the level shifter circuit, and consequentially avoiding any crowbar current. One disadvantage of using a reset generator, however, is the loss of the actual state of signal 1 at the time Vdd1 is powered off.
In general, it may be beneficial to provide a simple and versatile solution to latch the digital signals when transferring data (and providing signals) from one supply domain to another supply domain, especially when one of the supply domains is powered off, while preserving the state of the signals at the interface between the logic circuits in the respective different supply domains, and simultaneously reducing or completely eliminating crowbar current. Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.